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HFA1130/883
July 1994
Output Clamping, 850MHz Current Feedback Amplifier
Description
The HFA1130/883 is a high speed, wideband current feedback amplifier featuring programmable output clamps. Built with Intersil' proprietary complementary bipolar UHF-1 process, it is the fastest monolithic amplifier available from any semiconductor manufacturer. This amplifier is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overdrive recovery times. The output clamp function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation following an overdrive condition. The HFA1130/883's wide bandwidth, fast settling characteristic, and low output impedance, coupled with the output clamping ability, make this amplifier ideal for driving fast A/D converters. Component and composite video systems will also benefit from this amplifier's performance, as indicated by the excellent gain flatness, and 0.03%/0.05 Degree Differential Gain/ Phase specifications (RL = 75).
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * User Programmable Output Voltage Clamps * Low Distortion (HD3, 30MHz) . . . . . . . . . . -84dBc (Typ) * Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ) * Very High Slew Rate . . . . . . . . . . . . . . . 2300V/s (Typ) * Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 11ns (Typ) * Excellent Gain Flatness (to 50MHz) . . . . . 0.05dB (Typ) * High Output Current . . . . . . . . . . . . . . . . . . 65mA (Typ) * Fast Overdrive Recovery. . . . . . . . . . . . . . . . <1ns (Typ)
Applications
* Residue Amplifier * Video Switching and Routing * Pulse and Video Amplifiers * Wideband Amplifiers * RF/IF Signal Processing * Flash A/D Driver * Medical Imaging Systems
Ordering Information
PART NUMBER HFA1130MJ/883 HFA1130ML/883 TEMPERATURE RANGE -55oC -55oC to to +125oC +125oC PACKAGE 8 Lead CerDIP 20 Lead Ceramic LCC
Pinouts
HFA1130/883 (CERDIP) TOP VIEW
NC
HFA1130/883 (CLCC) TOP VIEW
NC NC NC 20 NC 19 18 VH 17 V+ 16 NC 15 OUT 14 NC 9 NC 10 V11 VL 12 NC 13 NC
NC -IN +IN V-
1 2 3 4
8
VH V+ OUT -IN 5 6 7 8 VL NC +IN NC NC 4
3
2
1
+
7 6 5
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number
3-204
511082-883 File Number 3625.1
Specifications HFA1130/883
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VVoltage at VH or VL Terminal . . . . . . . . . . . . . .(V+) + 2V to (V-) - 2V Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .55mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2000V Storage Temperature Range . . . . . . . . . . . . . . -65oC TA +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Thermal Information
Thermal Resistance JA JC CerDIP Package . . . . . . . . . . . . . . . . . . . 115oC/W 30oC/W Ceramic LCC Package . . . . . . . . . . . . . . 75oC/W 23oC/W Maximum Package Power Dissipation at +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W Package Power Dissipation Derating Factor above +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mW/oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Operating Temperature Range . . . . . . . . . . . . .-55oC TA +125oC RL 50
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = 5V, AV = +1, RF = 510, RSOURCE = 0, RL = 100, VOUT = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 1 2, 3 Common Mode Rejection Ratio Power Supply Rejection Ratio CMRR VCM = 2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V VSUP = 1.25V V+ = 6.25V, V- = -5V V+ = 3.75V, V- = -5V VSUP = 1.25V V+ = 5V, V- = -6.25V V+ = 5V, V- = -3.75V VCM = 0V VCM = 2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V Note 1 VCM = 0V VCM = 2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V VSUP = 1.25V V+ = 6.25V, V- = -5V V+ = 3.75V, V- = -5V VSUP = 1.25V V+ = 5V, V- = -6.25V V+ = 5V, V- = -3.75V AV = -1 RL =100 AV = -1 RL =100 VIN = 3.5V VIN = -3V VIN =+3.5V VIN = +3V 1 2, 3 1 2, 3 1 2, 3 1 2, 3 CMSIBP 1 2, 3 1 2, 3 Inverting Input (-IN) Current -IN Current Common Mode Sensitivity -IN Current Power Supply Sensitivity IBSN CMSIBN 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC MIN -6 -10 40 38 45 42 45 42 -40 -65 25 20 -50 -75 3 2.5 MAX 6 10 40 65 40 50 50 75 7 10 15 27 15 27 -3 -2.5 UNITS mV mV dB dB dB dB dB dB A A A/V A/V k k A A A/V A/V A/V A/V A/V A/V V V V V
PARAMETERS Input Offset Voltage
SYMBOL VIO
CONDITIONS VCM = 0V
PSRRP
+25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC
PSRRN
Non-Inverting Input (+IN) Current +IN Current Common Mode Sensitivity +IN Resistance
IBSP
+RIN
PPSSIBN
NPSSIBN
Output Voltage Swing
VOP100 VON100
+25oC +125oC, -55oC +25oC +125oC, -55oC
Spec Number 3-205
511082-883
Specifications HFA1130/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = 5V, AV = +1, RF = 510, RSOURCE = 0, RL = 100, VOUT = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 1, 2 3 1, 2 3 1, 2 3 -IOUT Quiescent Power Supply Current ICC IEE Clamp Accuracy VHCLMP VLCLMP Clamp Input Current VHBIAS VLBIAS NOTES: 1. Guaranteed from +IN Common Mode Rejection Test, by: +RIN = 1/CMSIBP . 2. Guaranteed from VOUT Test with RL = 50, by: IOUT = VOUT/50. Note 2 RL = 100 RL = 100 AV = -1, VIN = -2V VH = 1V AV = -1, VIN = +2V VL = -1V VH = 1V VL = -1V 1, 2 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 LIMITS TEMPERATURE +25oC, +125oC -55oC +25oC, +125oC -55oC +25oC, +125oC -55oC +25oC, +125oC -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2.5 1.5 50 30 14 -26 -33 -125 -200 -125 -200 -200 -300 MAX -2.5 -1.5 -50 -30 26 33 -14 125 200 125 200 200 300 UNITS V V V V mA mA mA mA mA mA mA mA mV mV mV mV A A A A
PARAMETERS Output Voltage Swing
SYMBOL VOP50 VON50
CONDITIONS AV = -1 RL = 50 AV = -1 RL = 50 Note 2 VIN = -3V VIN = -2V VIN = +3V VIN = +2V
Output Current
+IOUT
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = 5V, AV = +2, RF = 360, RL = 100, Unless Otherwise Specified. LIMITS PARAMETERS -3dB Bandwidth SYMBOL BW(-1) BW(+1) BW(+2) Gain Flatness GF30 GF50 GF100 CONDITIONS AV = -1, RF = 430 VOUT = 200mVP-P AV = +1, RF = 510 VOUT = 200mVP-P AV = +2, VOUT = 200mVP-P AV = +2, RF = 510, f 30MHz VOUT = 200mVP-P AV = +2, RF = 510, f 50MHz VOUT = 200mVP-P AV = +2, RF = 510, f 100MHz, VOUT = 200mVP-P NOTES 1 1 1 1 1 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN 300 550 350 MAX 0.04 0.10 0.30 UNITS MHz MHz MHz dB dB dB
Spec Number 3-206
511082-883
Specifications HFA1130/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = 5V, AV = +2, RF = 360, RL = 100, Unless Otherwise Specified. LIMITS PARAMETERS Slew Rate SYMBOL +SR(+1) -SR(+1) +SR(+2) -SR(+2) Rise and Fall Time TR TF Overshoot +OS -OS Settling Time TS(0.1) TS(0.05) 2nd Harmonic Distortion HD2(30) HD2(50) HD2(100) 3rd Harmonic Distortion HD3(30) HD3(50) HD3(100) NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot-to-lot and within lot variation. 2. Measured between 10% and 90% points. 3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to Performance Curves. CONDITIONS AV = +1, RF = 510 VOUT = 5VP-P AV = +1, RF = 510 VOUT = 5VP-P AV = +2, VOUT = 5VP-P AV = +2, VOUT = 5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, RF = 510 VOUT = 2V to 0V, to 0.1% AV = +2, RF = 510 VOUT = 2V to 0V, to 0.05% AV = +2, f = 30MHz VOUT = 2VP-P AV = +2, f = 50MHz VOUT = 2VP-P AV = +2, f = 100MHz VOUT = 2VP-P AV = +2, f = 30MHz VOUT = 2VP-P AV = +2, f = 50MHz VOUT = 2VP-P AV = +2, f = 100MHz VOUT = 2VP-P NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 3 1, 3 1 1 1 1 1 1 1 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 1200 1100 1650 1500 MAX 1 1 25 20 20 33 -48 -45 -35 -65 -60 -40 UNITS V/s V/s V/s V/s ns ns % % ns ns dBc dBc dBc dBc dBc dBc
TABLE 4.
ELECTRICAL TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1) 1 1 (Note 1), 2, 3 1, 2, 3 1
MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 1. PDA applies to Subgroup 1 only.
Spec Number 3-207
511082-883
HFA1130/883 Die Characteristics
DIE DIMENSIONS: 63 x 44 x 19 mils 1 mils 1600 x 1130 x 483m 25.4m METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA GLASSIVATION: Type: Nitride Thickness: 4kA 0.5kA WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 at 47.5mA TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA
Metallization Mask Layout
HFA1130/883 +IN
-IN
V-
VL
BAL
BAL
VH
V+
OUT
Spec Number 3-208
511082-883
HFA1130/883 Test Circuit (Applies to Table 1)
NC VL 0.1 K3 0.1 50
V+ ICC VIN K1 NC K2 = POSITION 1: 0.1 VX VIO = 100 VX x100 K2 K2 = POSITION 2: -IBIAS = VX 50K 200pF + 470pF
2 1
+
10
0.1
510 510 7 2 510 3+ 510 4 50 K5 0.1 100K (0.01%) + 10 0.1 NC K4 + HA-5177 VVH 0.1 IEE 0.1 DUT 8 100 100 5 6 1K VOUT
0.1 0.1
0.1 100
+IBIAS =
VZ 100K VZ
NOTE: All Resistors = 1% () All Capacitors = 10% (F) Unless Otherwise Noted Chip Components Recommended Terminal Numbers Refer to CDIP Package
Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3) AV = +1 TEST CIRCUIT
V+ VOUT 50 2 50
AV = +2 TEST CIRCUIT
V+ VOUT RF 50 360 RG 360 2 50
VIN RS 50 RF
+ -
VIN RS 50
+ -
510 VV-
NOTE: VS = 5V, AV = +1 RS = 50 RL = 100 For Small and Large Signals
NOTE: VS = 5V, AV = +2 RS = 50 RL=100 For Small and Large Signals
LARGE SIGNAL WAVEFORM
VOUT +2.5V 90% 90% +2.5V VOUT +250mV
SMALL SIGNAL WAVEFORM
+250mV
90%
90%
+SR -2.5V 10% 10%
-SR -2.5V
TR , +OS -250mV 10% 10%
TF , -OS -250mV
Spec Number 3-209
511082-883
HFA1130/883 Burn-In Circuits
HFA1130MJ/883 CERAMIC DIP
R3
R2 R1 D4 VD2 C2
1 2 3 4 +
8 7 6 5
D3 V+ C1 D1
NOTES: R1 = R2 = 1k, 5% (Per Socket) R3 = 10k, 5% (Per Socket) C1 = C2 = 0.01F (Per Socket) or 0.1F (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V 0.5V V- = -5.5V 0.5V HFA1130ML/883 CERAMIC LCC
R3
3 R2 4 5 R1 6 7 8
2
1 20 19 18 + 17 16 15 14 C1 D1 D3 V+
9 10 11 12 13 D4 VD2 C2
NOTES: R1 = R2 = 1k, 5% (Per Socket) R3 = 10k, 5% (Per Socket) C1 = C2 = 0.01F (Per Socket) or 0.1F (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V 0.5V V- = -5.5V 0.5V
Spec Number 3-210
511082-883
HFA1130/883 Packaging
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2 8
eA
D E e eA eA/2 L Q S1 S2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
e
DS
eA/2
c
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: Inch 11. Lead Finish: Type A. 12. Materials: Compliant to MIL-I-38535.
aaa bbb ccc M N
Spec Number 3-211
511082-883
HFA1130/883 Packaging (Continued)
D D3 j x 45o
J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER
INCHES SYMBOL A A1 B
E3 E
MILLIMETERS MIN 1.52 1.27 0.56 0.15 8.69 1.83 REF 0.56 9.09 MAX 2.54 2.23 0.71 NOTES 6, 7 7 4 2, 4 2 2 2 5 5 3 3 3
MIN 0.060 0.050 0.022 0.006 0.342
MAX 0.100 0.088 0.028 0.022 0.358
B
B1 B2 B3 D D1
0.072 REF
0.200 BSC 0.100 BSC 0.342 0.358 0.358 -
5.08 BSC 2.54 BSC 9.09 9.09 5.08 BSC 2.54 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.90 0.08 5 5 20 1.40 1.40 2.41 0.38 9.09 1.27 BSC 8.69
hx
45o
D2 D3 E
A A1 PLANE 2 PLANE 1
E1 E2 E3 e e1 h j
0.200 BSC 0.100 BSC 0.015 0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 5 5 20 0.055 0.055 0.095 0.015 0.358 0.050 BSC
L
e
L3
L L1 L2 L3 ND NE
E1
B1
B3
N NOTES:
E2
L2 B2
1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals.
L1
e1
D1
D2
2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.381mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 inch solder thickness on pads. 8. Lead Finish: Type A. 9. Materials: Compliant to MIL-I-38535.
Spec Number 3-212
511082-883
Semiconductor
HFA1130
Output Clamping, Ultra High Speed Current Feedback Amplifier
VSUPPLY = 5V, RF = 510, TA = +25oC, RL = 100, Unless Otherwise Specified. LARGE SIGNAL PULSE RESPONSE
1.2 0.9 OUTPUT VOLTAGE (V) 0.6 0.3 0 -0.3 -0.6 -0.9 -1.2 5ns/DIV 5ns/DIV AV = +2
DESIGN INFORMATION
August 1999
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
SMALL SIGNAL PULSE RESPONSE
120 90 OUTPUT VOLTAGE (mV) 60 30 0 -30 -60 -90 -120 AV = +2
UNCLAMPED PERFORMANCE
CLAMPED PERFORMANCE
IN 0V TO 0.5V
IN 0V TO 1V
OUT 0V TO 1V
OUT 0V TO 1V
AV = +2, VH = 2V, VL = -2V 10ns/DIV
AV = +2, VH = 1V, VL = -1V, 2X OVERDRIVE 10ns/DIV
Spec Number 3-213
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = 5V, RF = 510, TA = +25oC, RL = 100, Unless Otherwise Specified.
(Continued)
NON-INVERTING FREQUENCY RESPONSE
0 GAIN (dB) NORMALIZED -3 -6 -9 -12 VOUT = 200mVP-P PHASE 0 AV = +1 AV = +2 AV = +6 AV = +11 0.3 1 10 100 FREQUENCY (MHz) -90 GAIN GAIN (dB) NORMALIZED AV = +1 PHASE (DEGREES) AV = +2 AV = +6 AV = +11 0 -3 -6 -9 -12 VOUT = 200mVP-P AV = -1 PHASE (DEGREES) PHASE (DEGREES) 1K AV = -5 AV = -10 AV = -20 PHASE 180 AV = -1 AV = -5 AV = -10 AV = -20 0.3 1 10 100 FREQUENCY (MHz) 90 0 -90 -180 1K
INVERTING FREQUENCY RESPONSE
GAIN
-180 -270 -360 1K
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
+6 +3 0 GAIN (dB) -3 -6 PHASE RL = 100 RL = 50 RL = 50 RL = 100 AV = +1, VOUT = 200mVP-P RL = 1k PHASE (DEGREES) GAIN GAIN (dB) NORMALIZED
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
AV = +2, VOUT = 200mVP-P +3 0 -3 -6 PHASE RL = 50 RL = 100 RL = 1k RL = 100 RL = 1k 0.3 1 10 100 FREQUENCY (MHz) RL = 100 RL = 50 0 -90 -180 -270 -360 1K RL = 1k
GAIN
0 -90
RL = 1k RL = 100 RL = 1k 0.3 1 10 100 FREQUENCY (MHz)
-180 -270 -360 1K
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
+20 +10 0 GAIN (dB) -10 -20 -30 0.500VP-P 0.920VP-P 1.63VP-P AV = +1
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
+20 GAIN (dB) NORMALIZED +10 0 -10 -20 -30 1.00VP-P 1.84VP-P 3.26VP-P AV = +2 0.32VP-P
0.160VP-P
0.3
1
10 100 FREQUENCY (MHz)
1K
0.3
1
10 100 FREQUENCY (MHz)
Spec Number 3-214
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = 5V, RF = 510, TA = +25oC, RL = 100, Unless Otherwise Specified.
(Continued)
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
+20 GAIN (dB) NORMALIZED +10 0 -10 -20 -30 0.96VP-P TO 3.89VP-P BANDWIDTH (MHz) AV = +6 950 900 850 800 750 700 0.3 1 10 100 FREQUENCY (MHz) 1K -50 -25 0 +25 +50 +75 +100 +125
-3dB BANDWIDTH vs TEMPERATURE
AV = +1
TEMPERATURE (oC)
GAIN FLATNESS
AV = +2 DEVIATION (DEGREES) +2.0 +1.5 0 GAIN (dB) -0.05 -0.10 -0.15 -0.20 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 1 10 FREQUENCY (MHz) 100 0
DEVIATION FROM LINEAR PHASE
AV = +2
15
30
45 60 75 90 105 120 135 150 FREQUENCY (MHz)
SETTLING RESPONSE
AV = +2, VOUT = 2V INTERCEPT POINT (dBm) SETTLING ERROR (%) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6
3rd ORDER INTERMODULATION INTERCEPT
40 35 30 25 20 15 10 5 0 0 100 200 300 FREQUENCY (MHz) 400 2-TONE
-4
1
6
11
16 21 26 TIME (ns)
31
36
41
46
Spec Number 3-215
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = 5V, RF = 510, TA = +25oC, RL = 100, Unless Otherwise Specified.
(Continued)
2nd HARMONIC DISTORTION vs POUT
-30 -35 DISTORTION (dBc) DISTORTION (dBc) -40 -45 -50 -55 -60 -65 -70 -5 -3 -1 30MHz 50MHz 100MHz -30 -40 -50 100MHz -60 -70 -80 -90 30MHz -100 -110 1 5 7 9 11 3 OUTPUT POWER (dBm) 13 15 -5 -3 -1 1 3 5 7 9 11 13 15 50MHz
3rd HARMONIC DISTORTION vs POUT
OUTPUT POWER (dBm)
OVERSHOOT vs INPUT RISE TIME
38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 35 AV = +1 VOUT = 1VP-P OVERSHOOT (%) 30 25
OVERSHOOT vs INPUT RISE TIME
RF = 360 VOUT = 2VP-P
AV = +2
OVERSHOOT (%)
RF = 360 20 15 10 5 0 RF =510 VOUT = 1VP-P VOUT = 0.5VP-P
RF = 360 VOUT = 1VP-P
VOUT = 0.5VP-P
VOUT = 2VP-P
RF = 510 VOUT = 2VP-P VOUT = 0.5VP-P RF = 510
100 200 300 400 500 600 700 800 900 1000 INPUT RISE TIME (ps)
100 200 300 400 500 600 700 800 900 1000 INPUT RISE TIME (ps)
OVERSHOOT vs FEEDBACK RESISTOR
36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 25 AV = +2, tR = 200ps, VOUT = 2VP-P 24 SUPPLY CURRENT (mA) 23 22 21 20 19 18
SUPPLY CURRENT vs TEMPERATURE
OVERSHOOT (%)
360
400
440 480 520 560 600 FEEDBACK RESISTOR ()
640
680
-60
-40
-20
0 +20 +40 +60 +80 +100 +120 TEMPERATURE (oC)
Spec Number 3-216
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = 5V, RF = 510, TA = +25oC, RL = 100, Unless Otherwise Specified.
(Continued)
SUPPLY CURRENT vs SUPPLY VOLTAGE
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3
VIO AND BIAS CURRENTS vs TEMPERATURE
45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
INPUT OFFSET VOLTAGE (mV)
SUPPLY CURRENT (mA)
VIO
-IBIAS
5
6 7 8 9 TOTAL SUPPLY VOLTAGE (V+ - V-, V)
10
-60 -40 -20
0 +20 +40 +60 +80 +100+120 TEMPERATURE (oC)
OUTPUT VOLTAGE vs TEMPERATURE
3.7 3.6 OUTPUT VOLTAGE (V) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 TEMPERATURE (oC) 0 100 | - VOUT | AV = -1, RL = 50 +VOUT NOISE VOLTAGE (nV/Hz) 30 25 20 15 10 5
INPUT NOISE vs FREQUENCY
300 275 250 225 200 175 150 125 100 75 ENI INIINI+ 1K 10K FREQUENCY (Hz) 100K 50 25 0 NOISE CURRENT (pA/Hz)
NON-LINEARITY NEAR CLAMP VOLTAGE
20 15 VOUT - (AV * VIN) (mV) 10 5 0 -5 -10 -15 -20 -3 VH = 1V VH = 2V VH = 3V VL = -3V VL = -2V VL = -1V AV = -1, RL = 100
-2
-1
0 AV * VIN (V)
1
2
3
Spec Number 3-217
511082-883
BIAS CURRENTS (A)
+IBIAS
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Application Information
Optimum Feedback Resistor The enclosed plots of inverting and non-inverting frequency response illustrate the performance of the HFA1130 in various gains. Although the bandwidth dependency on closed loop gain isn't as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier's unique relationship between bandwidth and RF . All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier's bandwidth is inversely proportional to RF . The HFA1130 design is optimized for a 510 RF at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so RF can be decreased in a tradeoff of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth.
GAIN (ACL) -1 +1 +2 +5 +10 +19 RF () 430 510 360 150 180 270 BANDWIDTH (MHz) 580 850 670 520 240 125
recommended that the ground plane be removed under traces connected to -IN, and connections to -IN should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 850MHz. By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve. For example, at AV = +1, RS = 50, CL = 30pF, the overall bandwidth is limited to 300MHz, and bandwidth drops to 100MHz at AV = +1, RS = 5, CL = 340pF.
50 45 40 35 RS () AV = +1
PC Board Layout
The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. To this end, it is
30 25 20 15 10 5 A = +2 V 0 0 40 80 120 160 200 240 280 320 360 400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1130 may be evaluated using the HFA11XX Evaluation Board. The layout and schematic of the board are shown in Figure 2. To order evaluation boards, please contact your local sales office.
Spec Number 3-218
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
V+
TOP LAYOUT
QP3 VH 1 +IN OUT V+ VL VGND +IN QP1 VV+ QN1 QN5 QP2 QN2 ICLAMP Z +1 VH QN6 QP6 QP5 R1 50K (30K FOR VL) QP4
BOTTOM LAYOUT
QN3
QN4
VRF (EXTERNAL) VOUT
-IN
FIGURE 3. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
Clamp Circuitry Figure 3 shows a simplified schematic of the HFA1130 input stage, and the high clamp (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of:
VH
500 R1 1 50 IN 0.1F -5V 2 3 4 10F
500
(V-IN - VOUT)/RF + V-IN / RG
8 7 50 6 5 GND GND OUT VL 0.1F 10F +5V
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
where RG is the gain setting resistor from -IN to GND. This current is mirrored onto the high impedance node (Z) by QX3 - QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches it's quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. Tracing the path from VH to Z illustrates the effect of the clamp voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5. QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5's base voltage + 2VBE (QP5 and QN5). Thus, QP5 clamps node Z whenever Z reaches VH . R1 provides a pull-up network to ensure functionality with the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by VL.
Clamp Operation
General The HFA1130 features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the VH and VL terminals (DIP pins 8 and 5) of the amplifier. VH sets the upper output limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL ( the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs.
Spec Number 3-219
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
When the output is clamped, the negative input continues to source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as: ICLAMP = (V-IN - VOUT CLAMPED) / RF + V-IN / RG. As an example, a unity gain circuit with VIN = 2V, VH = 1V, and RF = 510 would have ICLAMP = (2V - 1V) / 510 + 2V / = 1.96mA. Note that Icc will increase by ICLAMP when the output is clamp limited. Clamp Accuracy The clamped output voltage will not be exactly equal to the voltage applied to VH or VL Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 3, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP . VBE increases as ICLAMP increases, causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT CLAMPED) and RF , so clamp accuracy degrades as the overdrive increases, and as RF decreases. As an example, the specified accuracy of 60mV for a 2X overdrive with RF = 510 degrades to 220mV for RF = 240 at the same overdrive, or to 250mV for a 3X overdrive with RF = 510. Consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity. The "Nonlinearity Near Clamp Voltage" curve in the data sheet illustrates the impact of several clamp levels on linearity.
Clamp Range Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HFA1130 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won't be in a DC output voltage from an AC input signal. A 150mV - 200mV AC signal will still be present at the output. Recovery from Overdrive The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP / AVCL) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of "Unclamped Performance" and "Clamped Performance" highlight the HFA1130's subnanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 4.0ns for the unclamped pulse, and 4.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1130 propagation delay is 500ps.
Spec Number 3-220
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = 5V, RF = 360, AV = +2V/V, RL = 100, Unless Otherwise Specified PARAMETERS Input Offset Voltage * Average Offset Voltage Drift VIO CMRR VIO PSRR +Input Current * Average +Input Current Drift -Input Current * Average -Input Current Drift +Input Resistance -Input Resistance Input Capacitance Input Noise Voltage * +Input Noise Current * -Input Noise Current * Input Common Mode Range Open Loop Transimpedance Output Voltage AV = -1 AV = -1, RL = 100 AV = -1, RL = 100 Output Current * AV = -1, RL = 50 AV = -1, RL = 50 DC Closed Loop Output Resistance Quiescent Supply Current * -3dB Bandwidth * RL = Open AV = -1, RF = 430, VOUT = 200mVP-P AV = +1, RF = 510, VOUT = 200mVP-P AV = +2, RF = 360, VOUT = 200mVP-P Slew Rate AV = +1, RF = 510, VOUT = 5VP-P AV = +2, VOUT = 5VP-P Full Power Bandwidth Gain Flatness * VOUT = 5VP-P To 30MHz, RF = 510 To 50MHz, RF = 510 To 100MHz, RF = 510 Linear Phase Deviation * 2nd Harmonic Distortion * To 100MHz, RF = 510 30MHz, VOUT = 2VP-P 50MHz, VOUT = 2VP-P 100MHz, VOUT = 2VP-P 3rd Harmonic Distortion * 30MHz, VOUT = 2VP-P 50MHz, VOUT = 2VP-P 100MHz, VOUT = 2VP-P +25oC f = 100kHz f = 100kHz f = 100kHz VCM = 0V Versus Temperature VCM = 2V VS = 1.25V VCM = 0V Versus Temperature VCM = 0V Versus Temperature VCM = 2V CONDITIONS TEMPERATURE +25oC Full +25oC +25 C +25oC Full +25oC Full +25oC +25oC +25oC +25oC +25oC +25 C Full +25 C +25oC Full to +125oC -55oC to 0oC +25oC Full +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o o o
TYPICAL 2 10 46 50 25 40 12 40 50 16 2.2 4 18 21 3.0 500 3.3 3.0 65 50 0.1 24 580 850 670 1500 2300 220 0.014 0.05 0.14 0.6 -55 -49 -44 -84 -70 -57
UNITS mV V/oC dB dB A nA/oC A nA/oC k pF nV/Hz pA/Hz pA/Hz V k V V mA mA mA MHz MHz MHz V/s V/s MHz dB dB dB Degrees dBc dBc dBc dBc dBc dBc
Spec Number 3-221
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = 5V, RF = 360, AV = +2V/V, RL = 100, Unless Otherwise Specified PARAMETERS 3rd Order Intercept * 1dB Compression Reverse Isolation (S12) CONDITIONS 100MHz, RF = 510 100MHz, RF = 510 40MHz, RF = 510 100MHz, RF = 510 600MHz, RF = 510 Rise & Fall Time VOUT = 0.5VP-P VOUT = 2VP-P Overshoot * Settling Time * VOUT = 0.5VP-P, Input tR/tF = 550ps To 0.1%, VOUT = 2V to 0V, RF = 510 To 0.05%, VOUT = 2V to 0V, RF = 510 To 0.02%, VOUT = 2V to 0V, RF = 510 Differential Gain Differential Phase Overdrive Recovery Time (2X Overdrive) Clamp Accuracy Clamped Overshoot Negative Clamp Range (VL) Positive Clamp Range (VH) Clamp Input Bias Current Clamp Input Bandwidth AV = +2, RL = 75, NTSC AV = +2, RL = 75, NTSC RF = 510, VIN = 1V, VH = +1V, VL = -1V AV = -1, RF = 510, VIN = 2V, VH = +1V, VL = -1V RF = 510, VIN = 1V, VH = +1V, VL = -1V, Input tR / tF = 2ns RF = 510 RF = 510 VH = +1V, VL = -1V VIN = 100mV, VH or VL = 100mVP-P TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o
TYPICAL 30 20 -70 -60 -32 500 800 11 11 19 34 0.03 0.05 750 60 4 -5.0 to +2.0 -2.0 to +5.0 50 500
UNITS dBm dBm dB dB dB ps ps % ns ns ns % Degrees ps mV % V V A MHz
*See Typical Performance Curves For More Information
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Spec Number 3-222
511082-883

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